1. Field of the Invention
The present invention relates to an optical detection apparatus and a liquid crystal display device using the same, and more particularly to an optical detection apparatus and a liquid crystal display device and a driving method using the apparatus for automatically adjusting a light amount irradiated onto a liquid crystal display panel.
2. Discussion of the Related Art
A liquid crystal display device (LCD) controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. An active matrix type of liquid crystal display device having a switching device provided for each liquid crystal cell is particularly well suited for displaying moving pictures through active control of the switching devices. The primary switching device used for active matrix liquid crystal display devices is the thin film transistor (hereinafter, referred to as “TFT”) as shown in FIG. 1.
As shown in FIG. 1, in a typical active matrix LCD device digital input data is converted into an analog data voltage using a gamma reference voltage and the analog data voltage is supplied to a data line DL while a scanning pulse is supplied to a gate line GL resulting in charging a liquid crystal cell Clc with the analog data voltage.
A gate electrode of the TFT is connected to the gate line GL, while a source electrode of the TFT is connected to the data line DL. Further, a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and to one electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
The storage capacitor Cst is charged by a data voltage fed from the data line DL when the TFT is turned-on and maintains the data voltage at the liquid crystal cell Clc until a new data voltage is feed from the data line DL.
When the scanning pulse is applied to a gate line GL, the TFT is turned on to provide a channel between the source electrode and the drain electrode of the TFT to connect a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. The alignment of the liquid crystal molecules of the liquid crystal cell is varied by an electric field generated between the pixel electrode and the common electrode to modulate light transmitted through the liquid crystal display device to display an image.
A liquid crystal display device of the related art including pixels having the above-mentioned structure will be described with reference to FIG. 2.
FIG. 2 is a block diagram showing a configuration of a related art liquid crystal display device.
As shown in FIG. 2, the related art liquid crystal display device 100 includes: a liquid crystal display panel 110 provided with a thin film transistor (TFT) for driving the liquid crystal cell Clc at crossings of data lines DL1 to DLm and gate lines GL1 to GLn; a data driver 120 for supplying a data to the data lines DL1 to DLm of the liquid crystal display panel 110; a gate driver 130 for supplying a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110; a gamma reference voltage generator 140 for generating a gamma reference voltage to supply to the data driver 120; a backlight assembly 150 for irradiating a light onto the liquid crystal display panel 110; an inverter 160 for applying an alternating current voltage and a current to the backlight assembly 150; a common voltage generator 170 for generating a common voltage Vcom for supply to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110, a gate driving voltage generator 180 for generating a gate high voltage VGH and a gate low voltage VGL for supply to the gate driver 130; and a timing controller 190 for controlling the data driver 120 and the gate driver 130.
The liquid crystal display panel 110 has liquid crystal injected or disposed between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn cross each other and are substantially perpendicular. Each crossing between one of the data lines DL1 to DLm and one of the gate lines GL1 to GLn defines a liquid crystal cell Clc has an associated TFT. The TFTs connect data on the data lines DL1 to DLm to liquid crystal cells Clc in response to the scanning pulse. The gate electrode of each TFT is connected to one of the gate lines GL1 to GLn while the source electrode thereof is connected to one of the data line DL1 to DLm. Further, the drain electrode of each TFT is connected to the pixel electrode of the associated liquid crystal cell Clc and to the storage capacitor Cst.
A TFT is turned-on in response to the scanning pulse applied to the gate electrode of the TFT via the gate lines GL1 to GLn. Upon turning-on of the TFT, a video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.
The data driver 120 supplies data to the data lines DL1 to DLm in response to a data driving control signal DDC supplied from the timing controller 190. In particular, the data driver 120 samples and latches digital video data RGB fed from the timing controller 190, and converts the digital video data RGB into an analog data voltage capable of expressing a gray scale level at the liquid crystal cell Clc of the liquid crystal display panel 110 based on a gamma reference voltage from the gamma reference voltage generator 140. The data driver supplies the analog digital video data to the data lines DL1 to DLm.
The gate driver 130 generates a scanning pulse, (i.e. gate pulse) in response to a gate driving control signal GDC and a gate shift clock GSM supplied from the timing controller 190, the scanning pulse to be sequentially supplied to the gate lines GL1 to GLn. The gate driver 130 establishes a high level voltage and a low level voltage for the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.
The gamma reference voltage generator 140 receives a high-level supply voltage VDD for generating a positive gamma reference voltage and a negative gamma reference voltage and outputs the positive and negative gamma reference voltages to the data driver 120.
The backlight assembly 150 is provided at the rear side of the liquid crystal display panel 110 and is energized by an alternating current (AC) voltage and current supplied from the inverter 160 to irradiate light onto each pixel of the liquid crystal display panel 110.
The inverter 160 converts a rectangular wave signal generated within the inverter into a triangular wave signal and then compares the triangular wave signal with a direct current power voltage VCC to generate a burst dimming signal proportional to a result of the comparison. The burst dimming signal is supplied to a driving integrated circuit (IC) to control generation of the AC voltage and current within the inverter to be supplied to the backlight assembly 150.
The common voltage generator 170 receives a high-level power voltage VDD to generate a common voltage Vcom and supplies the common voltage Vcom to the common electrode of the liquid crystal cell Clc provided at each pixel of the liquid crystal display panel 110.
The gate driving voltage generator 180 is supplied with a high-level power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL and supplies the gate high voltage VGH and the gate low voltage VGL to the gate driver 130. The gate driving voltage generator 180 generates a gate high voltage VGH greater than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110 and a gate low voltage VGL less than then the threshold voltage of the TFT. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used to establish the high level voltage and the low level voltage of the scanning pulse generated by the gate driver 130, respectively.
The timing controller 190 supplies a digital video data RGB received from a source such as a digital video card to the data driver 120 and, at the same time, generates a data driving control signal DCC and a gate driving control signal GDC using horizontal/vertical synchronizing signals H and V in response to a clock signal CLK. The data driving control signal DCC and a gate driving control signal GDC are to be supplied to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, and a source output enable signal SOE. The gate driving control signal GDC includes a gate start pulse GSP and a gate output enable signal GOE.
Because the backlight assembly 150 is supplied with a constant current from the inverter 160, the backlight assembly emits light having a constant intensity regardless of the amount of ambient light in the environment of the liquid crystal display panel 110. However in a dark environment, a user may comfortably view an image displayed by the liquid crystal using a reduced amount of light from the backlight assembly 150. Accordingly, because the related art liquid crystal display device 100 irradiates a light having a constant intensity onto the liquid crystal display panel 110 regardless of brightness of the environment, an avoidably large amount of power may be consumed by the backlight assembly 150. Further, an image displayed at the liquid crystal display panel 110 may appear relatively dim when the environment surrounding the liquid crystal display panel 100 is brightly lit. Increasing the light intensity emitted onto the liquid crystal display panel 110 in a bright environment may provide a more comfortable viewing of the displayed image by users. However, because the related art liquid crystal display device 100 irradiates a light having a constant intensity onto the liquid crystal display panel 110, the related art liquid crystal display device 100 may not present a satisfactory image to the user in brightly lit environments.